INVERTED R-2R LADDER DAC PDF

The digital signal is represented with a binary code, which is a combination of bits 0 and 1. This chapter deals with Digital to Analog Converters in detail. In general, the number of binary inputs of a DAC will be a power of two. A weighted resistor DAC produces an analog output, which is almost equal to the digital binary input by using binary weighted resistors in the inverting adder circuit. Recall that the bits of a binary number can have only one of the two values. In the above circuit, the non-inverting input terminal of an op-amp is connected to ground.

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More specifically, the present invention is concerned with a compensated inverted R-2R ladder and compensation technique therefor. In this context, high performances DACs have become crucial building blocks. The current-steering-flash DAC architecture is the most popular architecture for its inherent speed potential.

Resolution of these converters is generally limited by component mismatches, thus, gradients and random device variations challenge the analog designers. In high resolution DACs, static specifications are reached via trimming, and dynamic performances are mostly determined by current-steering switch performances. On the one hand, mandatory presence of switches impacts static performances, and compensation techniques must be used to cancel the switches effects on linearity and gain.

On the other hand, dynamic performances are strongly dependent on switch design and operation. For high-speed conversion, current-steering flash-DACs are often favored among other architectures.

Current-steering prevents current sources from turning off and on with digital input variations. In flash-high-speed DACs, the resolution is mainly limited by the level of matching reached between all reference currents. The inverted R-2R ladder is a current-mode DAC architecture which can be trimmed to resolutions up to about bits. Considering the availability of these techniques to reach high-resolution, DAC designers are still faced with high-speed operation challenges.

Indeed, even though generating ratioed currents with high-accuracy and resolution is possible, steering them to the appropriate output at high-speed without affecting their accuracy is still challenging. Figure 1 of the appended drawings, which is labelled "Prior Art", schematically illustrates a classic inverted R-2R ladder resistor circuit 10 producing four 4 binary weighted currents necessary for a 4-bit DAC.

Normal DAC operation requires switches. For current-mode operation, currents in the above networks typically flow through single-pole-double-throw SPDT switches controlled by input bit values.

As can be better seen in Figure 2, which is also schematic and labelled "Prior Art", the switches exhibit a resistance value that must be considered in the resistance network for accurate current division. As will be understood by one skilled in the art, for the network to be precise, the resistance value of each switch must be different since the current flowing in the ladder 10 must be divided in two at each junction Therefore the equivalent resistance must be equal on both branches of each junction It is to be noted that, for illustration purpose, a resistance equivalent to Ron has been added to arm 26 of the R-2R ladder resistor circuit Considering switches are nMOS transistors operating in the triode region, one skilled in the art will understand that halving of the resistance can be obtained by changing the channel's dimensions.

Modifying effective channel length poses an additionnal challenge of controlling the apparent substrate bias that changes with channel position when transistors have different length.

Another solution for exact halving of the resistance of the nMOS transistor is obtained by doubling the transistor effective width. This conventional method however leads to very large transistors steering the currents of the MSBs.

The impact on switching speed increases with the resolution of the DAC and switch control requires added synchronization circuitry adapted to the binary sizing. SUMMARY OF THE INVENTION More specifically, in accordance with an illustrative aspect of the present invention, there is provided a R-2R ladder resistor circuit comprising: a reference voltage input; a line including an input node connected to the reference voltage input; the line including a plurality of arms connected in series with a node between each adjacent arm, each arm having an identical resistor assembly including a resistor R and a switch, the line also including an output node;.

According to another aspect of the present invention, there is provided an inverted R-2R ladder resistor circuit comprising a plurality of R arms and a plurality of 2R arms; the plurality of R arms and the plurality of 2R arms being arranged in a R-2R ladder configuration having a current output, wherein each R arm includes a resistor assembly defined by a resistor R and a switch and wherein each 2R arm includes two resistor assemblies connected in series and each being defined by a resistor R and a switch.

It is to be noted that the expression "ground" is to be construed herein and in the appended claims as both a conventional ground or a virtual ground. Other objects, advantages and features of the present invention will become more apparent upon reading of the following non-restrictive description of illustrative embodiments thereof, given by way of example only with reference to the accompanying drawings.

A technique to achieve this is to replace each resistor by a resistor assembly including a resistor and a switch, as will be described hereinbelow. Turning now to Figure 3 of the appended drawings, a R-2R ladder resistor circuit according to an illustrative embodiment of the present invention will be described. It is to be noted that the R-2R ladder resistor circuit is schematically illustrated in Figure 3.

Furthermore, even tough the R-2R ladder resistor circuit is a 4-bit R-2R ladder resistor circuit, it may be resized at will. The R-2R ladder resistor circuit includes a reference voltage input and a current output , a resistor line , a plurality of shunt arms and a supplemental shunt arm The resistor line includes an input node , connected to the reference voltage input , and three identical resistor assemblies , and separated by nodes and , and an output node Each resistor assembly includes a resistor having a resistance value R and a switch Each resistor assembly , provided between two nodes, may be viewed as an R arm of the R-2R ladder resistor circuit Each shunt arm is provided with a first end that is connected to a respective node , , and Each shunt arm includes a first resistor assembly and a serially connected second resistor assembly The first resistor assembly is identical to the resistor assemblies of the resistor line since it includes a resistor having a resistance value R and a switch The resistor defining the first end of the shunt arm The second resistor assembly includes a resistor having a resistance value R and a SPDT switch provided with two output terminals and defining the second end of the shunt arm The output terminal is connected to the current output while the output terminal is connected to the ground The supplemental shunt arm has a first end connected to the output node and a second end connected to the ground Between the first and second ends, the supplemental shunt arm includes two serially connected identical resistor assemblies and each including a resistor having a resistance value R and a switch , making them identical to the resistor assemblies , , and The shunt arms and the supplemental shunt arm may be viewed as 2R arms of the R-2R ladder resistor circuit It is to be noted that the switches which are part of the resistor asemblies , , , , and are so-called "dummy" switches since they are always in their conductive state.

It is to be noted that these dummy switches are so designed as to present the same resistance value than the SPDT switches of the resistor assemblies Optionally, the switches could be SPDT switches not shown identical to the switches with only one of their output terminal used.

One skilled in the art will understand that since each resistor assembly of the R-2R ladder resistor circuit includes a resistor having a equal resistance value R and an identical switch, the resistance value of each resistor assembly is identical and does not affect the accuracy of the current division at each node.

In other words, the effects of the SPDT switches are compensated by the use of resistor assemblies provided with switches having a resistance equivalent to the internal resistance of the SPDT switches in the R-2R ladder resistor circuit Futhermore, one skilled in the art will understand that since every resistor is identical and every switch is identical, it is easier to match the various elements.

It is to be noted that an accurate compensation of the SPDT switches via the dummy switches is obtained through a carefull biasing of these dummy switches.

As mentioned hereinabove, the R-2R ladders such as the R-2R ladder resistor circuit described hereinabove are particularly useful when used as DACs and could be used, for example, in automatic test equipments, data acquisition systems, industrial process control, instrumentation and digitally controlled calibration. The operation of a R-2R ladder resistor circuit is believed well known to those skilled in the art and will therefore not be discussed herein, for concision purpose.

It is to be understood that the invention is not limited in its application to the details of construction and parts illustrated in the accompanying drawings and described hereinabove. The invention is capable of other embodiments and of being practiced in various ways.

It is also to be understood that the phraseology or terminology used herein is for the purpose of description and not limitation. Hence, although the present invention has been described hereinabove by way of illustative embodiments thereof, it can be modified, without departing from the spirit, scope and nature of the subject invention as defined in the appended claims.

A compensated inverted R-2R ladder and a compensation technique therefor to compensate inverted R-2R ladders in view of using identical resistors and identical switches to facilitate sizing and matching is described herein.

A technique to achieve this is to replace each resistor of the inverted R-2R ladder by a resistor assembly including a resistor and a switch. A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of the resistor assembly of each arm of the line is a dummy switch always in a conducting state, each dummy switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm.

A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of the resistor assembly of each shunt arm is a dummy switch always in a conducting state; each dummy switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm. A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of each of the two identical resistor assemblies of the supplemental shunt arm is a dummy switch always in a conducting state, each dummy switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm.

A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of the resistor assembly of each arm of the line is a SPDT switch always in a conducting state; each such SPDT switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm.

A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of the resistor assembly of each shunt arm is a SPDT switch always in a conducting state, each such SPDT switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm. A R-2R ladder resistor circuit as recited in claim 1, wherein the switch of each of the two identical resistor assemblies of the supplemental shunt arm is a SPDT switch always in a conducting state, each such SPDT switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the second resistor assembly of each shunt arm.

An inverted R-2R ladder resistor circuit comprising a plurality of R arms and a plurality of 2R arms, the plurality of R arms and the plurality of 2R arms being arranged in a R-2R ladder configuration having a current output, wherein each R arm includes a resistor assembly defined by a resistor R and a switch and wherein each 2R arm includes two resistor assemblies connected in series and each being defined by a resistor R and a switch.

An inverted R-2R ladder resistor circuit as recited in claim 8, wherein the switch of one of said two resistor assemblies of the 2R arms is a SPDT switch. An inverted R-2R ladder resistor circuit as recited in claim 9, wherein each SPDT switch includes two output terminals, one output terminal of each SPDT switch being connected to the current output.

An inverted R-2R ladder resistor circuit as recited in claim 10, wherein the other output terminal of each SPDT switch being connected to ground. An inverted R-2R ladder resistor circuit as recited in claim 9, wherein the switch of the other of said two resistor assemblies of the 2R arms is a dummy switch always in a conducting state, said dummy switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the one of the resistor assemblies of the 2R arm.

An inverted R-2R ladder resistor circuit as recited in claim 9, wherein the switch of the other of said two resistor assemblies of the 2R arms is a SPDT switch always in a conducting state, said SPDT switch having an internal resistance equivalent to an internal resistance of the SPDT switch of the one of the two resistor assemblies of the 2R arm.

An inverted R-2R ladder resistor circuit as recited in claim 8, wherein the switch of the resistor assembly of each R arm is a dummy switch always in a conducting state. CA CAA1 en CAA1 en. USB2 en. Sahoo et al. DET9 en. Bastos et al. Kwak et al. Devices and methods for calibrating amplifier stages and for compensating for errors in amplifier stages of series-connected components.

Calibration method for a digital-to-analogue converter using an array of current sources. KRB1 en. EPB1 en. Digital-to-analog converter including current cell matrix with enhanced linearity and associated methods.

CAA en. USA en. USA1 en. USB1 en. Technique for improved linearity of high-precision, low-current digital-to-analog converters. EPA2 en. Apparatus and method for an improved subranging ADC architecture using ladder-flip bussing. Yu et al. Systems and methods for providing compact digitally controlled trim of multi-segment circuits.

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